passing - makefile variable substitution
Passing additional variables from command line to make (5)
From the manual:
Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. However, an explicit assignment in the makefile, or with a command argument, overrides the environment.
So you can do (from bash):
resulting in a variable
FOOBAR in your Makefile.
Can I pass variables to a GNU Makefile as command line arguments? In other words, I want to pass some arguments which will eventually become variables in the Makefile.
If you make a file called Makefile and add a variable like this $(unittest) then you will be able to use this variable inside the Makefile even with wildcards
I use BOOST_TEST and by giving a wildcard to parameter --run_test=$(unittest) then I will be able to use regular expression to filter out the test I want my Makefile to run
The simplest way is:
make foo=bar target
Then in your makefile you can refer to
$(foo). Note that this won't propagate to sub-makes automatically.
If you are using sub-makes, see this article: Communicating Variables to a Sub-make
There's another option not cited here which is included in the GNU Make book by Stallman and McGrath (see http://www.chemie.fu-berlin.de/chemnet/use/info/make/make_7.html). It provides the example:
archive.a: ... ifneq (,$(findstring t,$(MAKEFLAGS))) +touch archive.a +ranlib -t archive.a else ranlib archive.a endif
It involves verifying if a given parameter appears in
MAKEFLAGS. For example .. suppose that you're studying about threads in c++11 and you've divided your study across multiple files (
class01, ... ,
classNM) and you want to: compile then all and run individually or compile one at a time and run it if a flag is specified (
-r, for instance). So, you could come up with the following
CXX=clang++-3.5 CXXFLAGS = -Wall -Werror -std=c++11 LDLIBS = -lpthread SOURCES = class01 class02 class03 %: %.cxx $(CXX) $(CXXFLAGS) -o [email protected] $^ $(LDLIBS) ifneq (,$(findstring r, $(MAKEFLAGS))) ./[email protected] endif all: $(SOURCES) .PHONY: clean clean: find . -name "*.out" -delete
Having that, you'd:
- build and run a file w/
make -r class02;
- build all w/
- build and run all w/
make -r(suppose that all of them contain some certain kind of assert stuff and you just want to test them all)
Then use the variable,
$(ROOT_DIR) in the Makefile.