makefile shell - Passing additional variables from command line to make
set assign (7)
Can I pass variables to a GNU Makefile as command line arguments? In other words, I want to pass some arguments which will eventually become variables in the Makefile.
You have several options to set up variables from outside your makefile:
From environment - each environment variable is transformed into a makefile variable with the same name and value.
You may also want to set
--environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves use the
overridedirective . However, it's not recommended, and it's much better and flexible to use
?=assignment (the conditional variable assignment operator, it only has an effect if the variable is not yet defined):
Note that certain variables are not inherited from environment:
MAKEis gotten from name of the script
SHELLis either set within a makefile, or defaults to
/bin/sh(rationale: commands are specified within the makefile, and they're shell-specific).
From command line -
makecan take variable assignments as part of his command line, mingled with targets:
make target FOO=bar
But then all assignments to
FOOvariable within the makefile will be ignored unless you use the
overridedirective in assignment. (The effect is the same as with
-eoption for environment variables).
Exporting from the parent Make - if you call Make from a Makefile, you usually shouldn't explicitly write variable assignments like this:
# Don't do this! target: $(MAKE) -C target CC=$(CC) CFLAGS=$(CFLAGS)
Instead, better solution might be to export these variables. Exporting a variable makes it into the environment of every shell invocation, and Make calls from these commands pick these environment variable as specified above.
# Do like this CFLAGS=-g export CFLAGS target: $(MAKE) -C target
You can also export all variables by using
The simplest way is:
make foo=bar target
Then in your makefile you can refer to
$(foo). Note that this won't propagate to sub-makes automatically.
If you are using sub-makes, see this article: Communicating Variables to a Sub-make
Then use the variable,
$(ROOT_DIR) in the Makefile.
From the manual:
Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. However, an explicit assignment in the makefile, or with a command argument, overrides the environment.
So you can do (from bash):
resulting in a variable
FOOBAR in your Makefile.
Say you have a makefile like this:
action: echo argument is $(argument)
You would then call it
make action argument=something
If you make a file called Makefile and add a variable like this $(unittest) then you will be able to use this variable inside the Makefile even with wildcards
I use BOOST_TEST and by giving a wildcard to parameter --run_test=$(unittest) then I will be able to use regular expression to filter out the test I want my Makefile to run
import sys print("\n".join(sys.argv))
sys.argv is a list that contains all the arguments passed to the script on the command line.
import sys print(sys.argv[1:])