gnu-make in - What is the difference between the GNU Makefile variable assignments=, ?=,:=and+=?




target from (5)

Can anybody give a clear explanation of how variable assignment really works in Makefiles.

What is the difference between :

 VARIABLE = value
 VARIABLE ?= value
 VARIABLE := value
 VARIABLE += value

I have read the section in GNU Make's manual, but it still doesn't make sense to me.


Answers

I suggest you do some experiments using "make". Here is a simple demo, showing the difference between = and :=.

/* Filename: Makefile*/
x := foo
y := $(x) bar
x := later

a = foo
b = $(a) bar
a = later

test:
    @echo x - $(x)
    @echo y - $(y)
    @echo a - $(a)
    @echo b - $(b)

make test prints:

x - later
y - foo bar
a - later
b - later bar

Check more elaborate explanation here


Using = causes the variable to be assigned a value. If the variable already had a value, it is replaced. This value will be expanded when it is used. For example:

HELLO = world
HELLO_WORLD = $(HELLO) world!

# This echoes "world world!"
echo $(HELLO_WORLD)

HELLO = hello

# This echoes "hello world!"
echo $(HELLO_WORLD)

Using := is similar to using =. However, instead of the value being expanded when it is used, it is expanded during the assignment. For example:

HELLO = world
HELLO_WORLD := $(HELLO) world!

# This echoes "world world!"
echo $(HELLO_WORLD)

HELLO = hello

# Still echoes "world world!"
echo $(HELLO_WORLD)

HELLO_WORLD := $(HELLO) world!

# This echoes "hello world!"
echo $(HELLO_WORLD)

Using ?= assigns the variable a value iff the variable was not previously assigned. If the variable was previously assigned a blank value (VAR=), it is still considered set I think. Otherwise, functions exactly like =.

Using += is like using =, but instead of replacing the value, the value is appended to the current one, with a space in between. If the variable was previously set with :=, it is expanded I think. The resulting value is expanded when it is used I think. For example:

HELLO_WORLD = hello
HELLO_WORLD += world!

# This echoes "hello world!"
echo $(HELLO_WORLD)

If something like HELLO_WORLD = $(HELLO_WORLD) world! were used, recursion would result, which would most likely end the execution of your Makefile. If A := $(A) $(B) were used, the result would not be the exact same as using += because B is expanded with := whereas += would not cause B to be expanded.


When you use VARIABLE = value, if value is actually a reference to another variable, then the value is only determined when VARIABLE is used. This is best illustrated with an example:

VAL = foo
VARIABLE = $(VAL)
VAL = bar

# VARIABLE and VAL will both evaluate to "bar"

When you use VARIABLE := value, you get the value of value as it is now. For example:

VAL = foo
VARIABLE := $(VAL)
VAL = bar

# VAL will evaluate to "bar", but VARIABLE will evaluate to "foo"

Using VARIABLE ?= val means that you only set the value of VARIABLE if VARIABLE is not set already. If it's not set already, the setting of the value is deferred until VARIABLE is used (as in example 1).

VARIABLE += value just appends value to VARIABLE. The actual value of value is determined as it was when it was initially set, using either = or :=.


In the above answers, it is important to understand what is meant by "values are expanded at declaration/use time". Giving a value like *.c does not entail any expansion. It is only when this string is used by a command that it will maybe trigger some globbing. Similarly, a value like $(wildcard *.c) or $(shell ls *.c) does not entail any expansion and is completely evaluated at definition time even if we used := in the variable definition.

Try the following Makefile in directory where you have some C files:

VAR1 = *.c
VAR2 := *.c
VAR3 = $(wildcard *.c)
VAR4 := $(wildcard *.c)
VAR5 = $(shell ls *.c)
VAR6 := $(shell ls *.c)

all :
    touch foo.c
    @echo "now VAR1 = \"$(VAR1)\"" ; ls $(VAR1)
    @echo "now VAR2 = \"$(VAR2)\"" ; ls $(VAR2)
    @echo "now VAR3 = \"$(VAR3)\"" ; ls $(VAR3)
    @echo "now VAR4 = \"$(VAR4)\"" ; ls $(VAR4)
    @echo "now VAR5 = \"$(VAR5)\"" ; ls $(VAR5)
    @echo "now VAR6 = \"$(VAR6)\"" ; ls $(VAR6)
    rm -v foo.c

Running make will trigger a rule that creates an extra (empty) C file, called foo.c but none of the 6 variables has foo.c in its value.


Here's how I do it.

One caveat is that I don't put any of my C++ source code in the build dir, since most of it is platform-independent. This just means that LOCAL_PATH is not a subdir of the project dir, and the only files in /jni are the 2 .mk files.

Anyway, here's a full top-level Android.mk and one of the included ones for a real project:

Top level:

LOCAL_PATH := $(abspath $(call my-dir)/../../../src)

# utility to create paths for included makefiles
local-rel-path = $(patsubst /%,%,$(subst $(LOCAL_PATH),,$(abspath $1)))

include $(CLEAR_VARS)

LOCAL_MODULE := NativeApp

LOCAL_LDLIBS := -lGLESv1_CM

# As opposed to "thumb"
LOCAL_ARM_MODE := arm

LOCAL_SRC_FILES :=

#
# includes
#
# Note that LOCAL_C_INCLUDE is relative to thr NDK root, unlike source paths
# (or you can just make 'em absolute)
#
STL_INC_DIR = /cygdrive/c/STLport-5.2.1/stlport

MY_LOCAL_C_INCLUDES := core satcalc bruce/bruce/inc bruce/gfx/inc bruce/ui/inc bruce/unzip bruce/libpng

LOCAL_C_INCLUDES := $(addprefix $(LOCAL_PATH)/,$(MY_LOCAL_C_INCLUDES)) $(STL_INC_DIR) 

ifeq ($(APP_OPTIM),debug)
# debug
LOCAL_CFLAGS = -DPLATFORM_ANDROID -D_DEBUG -fvisibility=hidden
else
#release
LOCAL_CFLAGS = -DPLATFORM_ANDROID -fvisibility=hidden
endif

LOCAL_STATIC_LIBRARIES := 

#
# Code
#
include $(LOCAL_PATH)/core/Android.mk
include $(LOCAL_PATH)/satcalc/Android.mk
include $(LOCAL_PATH)/bruce/bruce/src/Android.mk
include $(LOCAL_PATH)/bruce/gfx/src/Android.mk
include $(LOCAL_PATH)/bruce/ui/src/Android.mk
include $(LOCAL_PATH)/bruce/unzip/Android.mk
include $(LOCAL_PATH)/bruce/libpng/Android.mk

#
# Build it
#
include $(BUILD_SHARED_LIBRARY)

...and an included Android.mk:

MY_PATH = $(call my-dir)

MY_LOCAL = $(call local-rel-path, $(MY_PATH))

MY_SRC_FILES = Font.cpp Gfx2d_ogles.cpp SgaState.cpp \
        Sprite.cpp TImage.cpp TImageOgles.cpp 

LOCAL_SRC_FILES += $(addprefix $(MY_LOCAL)/,$(MY_SRC_FILES))




makefile gnu-make